|
Main publications
- Magnus Själander and Per Larsson-Edefors
"High-Speed and Low-Power Multipliers Using the Baugh-Wooley Algorithm and HPM Reduction Tree"
To appear at the 15th IEEE International Conference on Electronics, Circuits and Systems,
St. Julians, Malta, 31st August - 3 September, 2008
- Magnus Själander and Per Larsson-Edefors
"The Case for HPM-Based Baugh-Wooley Multipliers"
Department of Computer Science and Engineering, Chalmers University of Technology, Technical Report 08-8,
Göteborg, Sweden, March 4, 2008
- Martin Thuresson, Magnus Själander, Magnus Bjök, Lars Svensson,
Per Larsson-Edefors, and Per Stenstrom
"FlexCore: Utilizing Exposed Datapath Control for Efficient Computing"
To appear in Springer Journal of Signal Processing, 2008
- Martin Thuresson and Per Stenstrom
"Accommodation of the Bandwidth of Large Cache Blocks using Cache/Memory Link Compression"
To appear in International Conference on Parallel Processing, 2008
- Martin Thuresson and Per Stenstrom
"Memory Link Compression Schemes: A Value Locality Perspective"
IEEE Transactions on Computers, Volume 57, Issue 7, July 2008
- Martin Thuresson, Magnus Själander, Magnus Bjök, Lars Svensson,
Per Larsson-Edefors, and Per Stenstrom
"Utilizing Exposed Datapath for Efficient Computing"
Presented at International Symposium on Systems,
Architectures, MOdeling and Simulation (SAMOS VII) Samos, Greece, July 16-19, 2007.
- Magnus Själander, Per Larsson-Edefors, and Magnus Björk
"A Flexible Datapath Interconnect for Embedded Applications"
Presented at IEEE Computer Society Annual Symposium on VLSI,
Porto Alegre, Brazil, May 9-11 2007
- Magnus Björk, Magnus Själander, Lars Svensson, Martin Thuresson
John Hughes, Kjell Jeppson, Jonas Karlsson, Per Larsson-Edefors, Mary Sheeran, and Per Stenstrom
"Exposed datapath for efficient computing"
Presented at HiPEAC Workshop on Reconfigurable Computing Ghent, Belgium, January 28-30 2006.
- Magnus Björk, Magnus Själander, Lars Svensson, Martin Thuresson
John Hughes, Kjell Jeppson, Jonas Karlsson, Per Larsson-Edefors, Mary Sheeran, and Per Stenstrom
"Exposed datapath for efficient computing"
Technical Report 2006-20, Chalmers University of Technology, Department of Computer Science and Engineering, December 2006.
- Martin Thuresson and Per Stenstrom
"Scalable Value-Cache Based Compression Schemes for Multiprocessors"
Presented at International Symposium on Computer Architecture and High Performance Computing 2006
Ouro Preto, Brazil, Oct, 2006.
- Martin Thuresson
Licentiate thesis on "Compression Techniques for Code Size and Data Bandwidth Reduction"
ISSN: 1652-876X, Technical Report 14L, Chalmers University of Technology
- Magnus Själander
Licentiate thesis on Efficient Reconfigurable
Multipliers Based on the Twin-Precision Technique
Defended on March 2, 2006 at 13.15 in Rännvägen ES53.
ISSN: 1652-876X, Technical Report 12L, Chalmers University of Technology
- Magnus Själander, Martin Thuresson, Per Larsson-Edefors, and Per Stenström
FlexSoC - Past, Present & Future,
(Poster), ISBN: 90 382 0802 2
Presented at ACACES, L'Aquila, Italy, July 24-30, 2005.
- Magnus Själander, Mindaugas Drazdziulis, Per Larsson-Edefors, and Henrik Eriksson
A Low-Leakage Twin-Precision Multiplier Using Reconfigurable Power Gating.
Presented at ISCAS, Kobe, Japan, May 23-26, 2005.
- Martin Thuresson and Per Stenstrom
Evaluation of Extended Dictionary-Based Static Code Compression Schemes.
Presented at Computer Frontiers 2005
Ischia, Italy, May 4-6th, 2005.
- Magnus Själander and Per Larsson-Edefors
A Power-Efficient and Versatile Modified-Booth Multiplier
Presented at SSoCC,
Tammsvik, Sweden, April 18-19, 2005.
- Magnus Själander, Henrik Eriksson, and Per Larsson-Edefors
An Efficient Twin-Precision Multiplier.
Presented at ICCD,
San Jose, California, Oct 11-13, 2004.
- John Hughes et al.
FlexSoC
Poster Presented at SSoCC,
Båstad, Sweden, April 13-14, 2004.
- John Hughes et al.
FlexSoC: Combining Flexibility and Efficiency in SoC Designs.
In Proceedings of the IEEE NorChip Conference,
Riga, Latvia, Nov 10-11, 2003.
Master's theses
- Jonas Ferry
A Comparison Between the two Synthesizable VHDL Models MIPS-RISC and MIPS-NISC
Master's Thesis,
Chalmers University,
February 2008.
- Erik Ryman
iFPGA Implmentation of a FlexCore Memory Environment
Master's Thesis,
Chalmers University,
December 2007.
- Martin Brink and Kristian Eklund
A Flexible FFT/DCT Engine Using the Twin-Precision Technique.
Master's Thesis,
Chalmers University,
March 2006.
- Jan Mårts and Tomas Carlqvist
A Hardware Audio Decoder Using Flexible Datapaths.
Master's Thesis,
Chalmers University,
March 2006.
- Michael Pellauer
CoreLoom: A Semantic Model for Fine-Grained Flexible Datapaths.
Master's Thesis,
Chalmers University,
May 2004.
Thesis,
presentation,
source code.
|
|
